// +FHDR------------------------------------------------------------
//                 Copyright (c) 2023 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : async_fifo_sync_path.v
// Author        : ICer
// Created On    : 2023-12-28 17:54
// Last Modified : 2023-12-28 18:12 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module async_fifo_sync_path #(
    //parameter
    parameter SYNC_CYC = 3,
    parameter WIDTH = 8
)( /*AUTOARG*/
   // Outputs
   out_data,
   // Inputs
   in_clk, in_rst_n, out_clk, out_rst_n, in_data
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input in_clk;
input in_rst_n;
input out_clk;
input out_rst_n;

input [WIDTH -1:0]in_data;
output[WIDTH -1:0]out_data;

// ----------------------------------------------------------------
// Wire declare
// ----------------------------------------------------------------

// ----------------------------------------------------------------
// AUTO declare
// ----------------------------------------------------------------
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/

// ----------------------------------------------------------------
// in_clk region
// ----------------------------------------------------------------
wire [WIDTH -1:0]in_data_gray;
reg  [WIDTH -1:0]in_data_gray_ff;
async_fifo_b2g_unit #(.WIDTH(WIDTH))
u_b2g(
  .binary(in_data),
  .gray(in_data_gray)     
);

always @(posedge in_clk or negedge in_rst_n) begin
  if(!in_rst_n) begin
    in_data_gray_ff <=  {WIDTH{1'b0}};
  end 
  else begin
    in_data_gray_ff <= in_data_gray;
  end
end

// ----------------------------------------------------------------
// sync
// ----------------------------------------------------------------
wire [WIDTH -1:0]out_data_gray;
genvar i;
generate
  for(i=0; i<WIDTH; i=i+1)begin: inst_rtl
    async_fifo_delay_unit #(
      .SYNC_CYC(SYNC_CYC))
    u_sync_cell(
      .clk(out_clk),
      .rst_n(out_rst_n),
      .in(in_data_gray_ff[i]),
      .out(out_data_gray[i])
    );
  end
endgenerate

// ----------------------------------------------------------------
// out_clk region
// ----------------------------------------------------------------
async_fifo_g2b_unit #(.WIDTH(WIDTH))
u_g2b(
  .gray(out_data_gray),
  .binary(out_data)
);

endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

